What is Embedded System?
Electrical control system which is designed to perform predefined specific function with combination of computer hardware and software
Acronym for Reduced Instruction Set Computer. A microprocessor that carries out fewer instructions than traditional microprocessors so that it can work more quickly.
An operating system designed specifically for use in real-time systems that should respond to external events within a short and predictable time frame.
kernel is an bridge between OS and Hardware. kernel is the heart the of OS( Operating System ), usually kernel only operate both the hardware and software, the operating system is nothing but wrapper of the kernel, through os user can achieve his operation easily ( user friendly ). OS is defines as interface between user and computer.
The Central Processing Unit (CPU), It contains instruction processing logic, instruction and data pointers, and an operand register. It directly accesses the high speed on-chip memory, which can store data or programs. Where larger amounts of memory are required, the processor can access memory via the External Memory Interface (EMI).
When system is powered on, the first piece of code (called boot-strapping) initializes basic hardware and then bring up OS kernel
A small amount (normally less than 1MB) of high-speed memory residing on or close to the CPU. Cache memory is fast memory that is used to hold the most recently accessed data in slower main memory. The idea is that frequently accessed data will stay in cache, which allows the CPU to access it more quickly, which means it doesn’t have to wait for the data to arrive.
Cache Write Policies
If data is written to the cache, at some point it must also be written to main memory. The timing of this write is known as the write policy.
- In a write-through cache, every write to the cache causes a write to main memory.
- Alternatively, in a write-back or copy-back cache, writes are not immediately mirrored to the main memory. Instead, the cache tracks which locations have been written over (these locations are marked dirty). The data in these locations are written back to the main memory only when that data is evicted from the cache. For this reason, a miss in a write-back cache may sometimes require two memory accesses to service: one to first write the dirty location to memory and then another to read the new location from memory.
In a shared memory multiprocessor with a separate cache memory for each processor , it is possible to have many copies of any one instruction operand : one copy in the main memory and one in each cache memory. When one copy of an operand is changed, the other copies of the operand must be changed also. Cache coherence is the discipline that ensures that changes in the values of shared operands are propagated throughout the system in a timely fashion.
Direct memory access (DMA) is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit (CPU).Without DMA, when the CPU is using programmed input/output, it is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With DMA, the CPU initiates the transfer, does other operations while the transfer is in progress, and receives an interrupt from the DMA controller when the operation is done. This feature is useful any time the CPU cannot keep up with the rate of data transfer, or where the CPU needs to perform useful work while waiting for a relatively slow I/O data transfer.
Flash memory is a type of constantly-powered nonvolatile memory that can be erased and reprogrammed in units of memory called blocks. It is a variation of electrically erasable programmable read-only memory (EEPROM) which, unlike flash memory, is erased and rewritten at the byte level, which is slower than flash memory updating.
SRAM Vs DRAM
SRAM (Static RAM) and DRAM (Dynamic RAM) holds data but in a different ways. DRAM requires the data to be refreshed periodically in order to retain the data. SRAM does not need to be refreshed as the transistors inside would continue to hold the data as long as the power supply is not cut off. This behavior leads to a few advantages, not the least of which is the much faster speed that data can be written and read.The additional circuitry and timing needed to introduce the refresh creates some complications that makes DRAM memory slower and less desirable than SRAM. One complication is the much higher power used by DRAM memory
Watch Dog Timer
A watchdog timer is a piece of hardware that can be used to automatically detect software anomalies and reset the processor if any occur. Generally speaking, a watchdog timer is based on a counter that counts down from some initial value to zero. The embedded software selects the counter’s initial value and periodically restarts it. If the counter ever reaches zero before the software restarts it, the software is presumed to be malfunctioning and the processor’s reset signal is asserted. The processor (and the embedded software it’s running) will be restarted as if a human operator had cycled the power.